• RTL/DV/PD/DFT/Layout

Location Bengaluru
Experience Range 1 - 20 Years

Functional Engineering Design / R&D
Job Description
About Us
ACL Digital is a design-led Digital Experience, Product Innovation, Solutions, and Consulting offerings leader. From strategy, to design, implementation, and management we help accelerate innovation and transform businesses. Keeping customer journeys and design at the core, it is committed to enable large Enterprises, SMBs and start-ups to transform. A pioneer in delivering Business Innovation, Integration and Transformation through disruptive technologies, ACL Digital brings in competitive advantage, innovation, and fresh perspectives to business challenges. With a multi-cultural and transnational talent and as part of the ALTEN Group comprising over 37,000 employees spread across more than 25 countries, it promotes a collaborative knowledge-building environment.
Roles and Responsibility

DFT Engineer responsible for implementing DFT / Test on complex IP and SOC for ASIC designs. Candidate needs to have a thorough knowledge on various DFT/Test architecture solutions. 


Responsibilities :

  • Exposure to Tessent tools and pattern generation/sim/debug and coverage improvement activities.
  • Very good knowledge on SCAN/ATPG/JTAG/MBIST.
  • Good knowledge about running tile level and chip level STA flows.
  • Experience with one or more chip tapeout that included full timing closure responsibility.
  • Proven experience in Scan insertion techniques at block level and Chip top level.
  • Proficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools).
  • Good Knowledge and understanding on JTAG.
  • Good hands on experience on Memory BIST generation, Insertion, verification on RTL/Netlist level.

Desired Skills :