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Roles and Responsibility
DFT Engineer responsible for implementing DFT / Test on complex IP and SOC for ASIC designs. Candidate needs to have a thorough knowledge on various DFT/Test architecture solutions.
Responsibilities :
- Exposure to Tessent tools and pattern generation/sim/debug and coverage improvement activities.
- Very good knowledge on SCAN/ATPG/JTAG/MBIST.
- Good knowledge about running tile level and chip level STA flows.
- Experience with one or more chip tapeout that included full timing closure responsibility.
- Proven experience in Scan insertion techniques at block level and Chip top level.
- Proficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools).
- Good Knowledge and understanding on JTAG.
- Good hands on experience on Memory BIST generation, Insertion, verification on RTL/Netlist level.
Desired Skills :