• PMIC HW Validation Engg

Location Bengaluru
Experience Range 2 - 5 Years

Job Description
About Us
ACL Digital is a design-led Digital Experience, Product Innovation, Solutions, and Consulting offerings leader. From strategy, to design, implementation, and management we help accelerate innovation and transform businesses. Keeping customer journeys and design at the core, it is committed to enable large Enterprises, SMBs and start-ups to transform. A pioneer in delivering Business Innovation, Integration and Transformation through disruptive technologies, ACL Digital brings in competitive advantage, innovation, and fresh perspectives to business challenges. With a multi-cultural and transnational talent and as part of the ALTEN Group comprising over 37,000 employees spread across more than 25 countries, it promotes a collaborative knowledge-building environment.
Roles and Responsibility
Must have BSEE in EE with 5-10 years of relevant experience:
Requirements :
Proficient on Synthesis, Static timing constraints , LEC/Formality 
Strong knowledge of SOC design methodologies and flows 
Good Knowledge of system-level architectures
Experience with Lint,  CDC and STA 
Work with RTL and DFT engineers, prepare SoC Top/Block level constraints 
Work closely with SOC Team to achieve full chip timing, power, physical closure 
Experience in timing & Functional ECO process 
Create/ work on designs using Low Power Design Methodology. 
Creates deliverables which do not require close review or supervision by a Senior Technical Lead. 
Experience with Perforce or similar revision control environment 
Excellent scripting skills in tcl/Perl/Shell.
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